A semiconductor memory device commonly comprises an array of rows and columns. Each intersection of the rows and columns defines a memory "cell". A cell stores either a logical `0` or a logical `1`. Associated with each column is a device which is used to detect changes in the logic state of the cells in that column. This device is usually called a sense amplifier because it "senses" a change in the logic state of the cell and amplifies it for transmission to the next stage of the circuit.
To perform this function, a sense amplifier must be able to distinguish between a `0` and a `1`. One of the problems associated with distinguishing a `1` is charge leakage. Over time, the voltage level in the cell decays. When the sense amplifier compares a decayed or stale `1` with a reference voltage that defines a clear `1`, the cell appears to the sense amplifier to be storing a `0`.
Several different techniques are available for performing sense amplification. One such technique uses what is known as a "sample-and-hold" function. According to this technique, the sense amplifier samples the memory cell and holds the sampled voltage for a precisely controlled period of time. At the end of the time span, the voltage will have become attenuated. By measuring the voltage attenuation, the circuit distinguishes a `0` from `1`. The measurement is performed by comparing the attenuated sample with another stable and known voltage level, often called the reference voltage Vref. A sampled voltage which is above the reference voltage Vref at the end of the time span is identified as a `1`; conversely, a sampled voltage which is below Vref is identified as a `0`. Since the measurement is done with respect to a reference voltage Vref, this type of device is called a reference voltage comparator.
One of the problems associated with this technique is the variability in the amount of attenuation. The sense amplifier is made to measure attenuation to a certain limit before the output will change to `0`. Due to variation in the time passing since the memory cell was last read, as well as variations in processing the device, the amount of attenuation occurring for a `1` is not always what the sense amplifier will identify as a `1`.
FIG. 1 shows a conventional level shifting sense amplifier. When the memory cell is storing a `1`, current drains from the power source 10 to ground 12. The input to the inverter 14 is held low; thus, the output is held high. When the cell is storing a `0`, no current flows. The input to the inverter stays high since transistor T.sub.1 is now off and the output of the inverter is low, i.e. `0`. This design, while instructive, is no longer widely used. The design requires extra dc power for the inverter and is overly sensitive to both positive going noise and fluctuations in the power supply.
FIG. 2 shows a conventional sense amplifier that uses "dummy cells". A dummy cell is a circuit which is a duplicate of the memory cell. It stores the voltage level of the memory cell from some prior time. This sense amplifier design is essentially of the sample-and-hold type. For a reference voltage, the sense amplifier uses the dummy cell voltage. The reference is thus highly dependent on processing variations. Nor does this design respond well to noise on the cell column lines. Dummy cell sense amplifiers are also undesirable due to their size and power needs. Normally, one column of dummy cells is required for each half of the memory array. Given the ever-increasing number of cells contained in state-of-the-art memory devices, this results in a constraint on the total "usable" memory that will fit on a semiconductor chip of limited size.
FIG. 3 shows a variation on the above-described conventional level shifting design. The FIG. 3 design, which uses a high trip inverter, includes a bias line and a precharge switch. Transistor 30 is turned on to raise the bias line to its upper limit. Transistor 32 holds the bias line high. Transistor 30 is turned off so that no current will drain from the power supply 34 to ground 36 when the cell is accessed. The input to the inverter 38 is thus a `1` and the output is a `0`. If the cell is storing a `0`, then no current will flow between node (39) and ground and the output of the inverter remains as it was, i.e. low. If the cell is storing a `1`, then current drains from the bias line through transistor 40 to ground. The bias line is thus "pulled" low by the cell and the output of the inverter 38 goes high, i.e. to `1`. This design is sensitive to noise and to charge remaining on the dataline from the last read cycle. The inverter 38 has a threshold voltage at which it responds to the input as if it were `1`. This threshold is sensitive to variations in processing the device.
FIG. 4 shows a variation of the "dummy cell" type of sensing amplifier. In the FIG. 4 circuit, a copy of the inverse of the voltage stored in a memory cell is retained for subsequent comparison with a reference. While this solution avoids some problems associated with sense amplifiers, it again requires chip area to house the dummy cells.
U.S. Pat. No. 4,301,518 entitled "Differential Sensing of Single Ended Memory Array" issued Nov. 17, 1981 to J. M. Klaas, discloses a differential sensing circuit for producing a data output. The Klaas sense circuit allows the array to be biased independent of the sense operation. A reference voltage is provided for direct comparison to the operating point of the selected column line, producing a differential voltage the polarity of which indicates the logic state of the selected cell.
U.S. Pat. No. 4,166,982 entitled "Logic Circuit Reference Electric Level Generating Circuitry", issued Sept. 4, 1979 to W. A. Christophersen, discloses the use of a reference voltage and/or current for distribution to a plurality of logical circuits on a semiconductor chip having of the order of a thousand such circuits thereon. An operational amplifier and evener circuitry drives the reference voltage distribution grid laid out over the semiconductor chip.
Examples of typical bipolar sense amplifiers are provided in U.S. Pat. No. 3,376,515 issued Apr. 2, 1968 to W. G. Dilley and U.S. Pat. No. 4,099,266 issued July 4, 1978 to C. Biggers. An example of reading or writing MTL (merged transistor logic) is disclosed in U.S. Pat. No. 4,330,853 issued May 18, 1982 to H. H. Heimeier et al.
In summary, prior art sense amplifiers are subject to several limitations. Reference voltages derived from power sources independent of the dataline are insensitive to variations in threshold voltages. Changes in the power sourcing the reference voltage can cause it to be unresponsive. Off-chip reference voltages are limited by exacting requirements for processing parameters, slight deviations in production proving fatal to accuracy. Also, speed limitations are present due to noise sensitivity, resulting in an inaccurate reading of the cell's memory.
Reference voltages generated from the dataline itself would not be subject to these limitations.